View ISL85402_2731895.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. 2.5a regulator with integrated high-side mosfet for synchronous buck or boost buck converter ISL85402 the ISL85402 is a synchronous buck controller with a 125m ? high-side mosfet and low-side driver integrated. the ISL85402 supports a wide input voltage range from 3v to 36v. regarding the output current capability from the thermal perspective, the ISL85402 can typically support co ntinuous load of 2.5a under conditions of 5v v out , v in range of 8v to 30v, 500khz, +85c ambient temperature with still air. for any specific application, the actual maximum output current de pends upon the die temperature not exceeding +125c with the power dissipated in the ic, which is related to input voltage, output voltage, duty cycle, switching frequency, board layout and ambient temperature, etc. refer to ?output current? on page 13 for more details. the ISL85402 has flexible sele ction of operation modes of forced pwm mode and pfm mode. in pfm mode, the quiescent input current is as low as 180a (auxvcc connected to v out ). the load boundary between pfm and pwm can be programmed to cover wide applications. the low-side driver can be either used to drive an external low-side mosfet for a synchronous buck, or left unused for a standard non-synchronous buck. the low-side driver can also be used to drive a boost converter as a pre-regulator followed by a buck controlled by the same ic, which greatly expands the operating input voltage range down to 3v or lower (refer to ?typical application schematic iii - boost buck converter? on page 5). the ISL85402 offers the most robust current protections. it uses peak current mode control with cycle-by-cycle current limiting. it is implemented with frequency foldback under current limit condition; beside s that, the hiccup overcurrent mode is also implemented to guarantee reliable operations under harsh short conditions. the ISL85402 has comprehensive protections against various faults including overvoltage and over-temperature protections, etc. features ? ultra wide input voltage range 3v to 36v ? optional mode operation - forced pwm mode - selectable pfm with programmable pfm/pwm boundary ? 300a ic quiescent current (pfm, no load); 180a input quiescent current (pfm, no load, v out connected to auxvcc) ? less than 3a standby input current (ic disabled) ? operational topologies -synchronous buck -non-synchronous buck - two-stage boost buck ? programmable frequency from 200khz to 2.2mhz and frequency synchronization capability ? 1% tight voltage regulation accuracy ? reliable overcurrent protection - temperature compensated current sense - cycle-by-cycle current limiting with frequency foldback - hiccup mode for worst case short condition ? 20 ld 4x4 qfn package ? pb-free (rohs compliant) applications ?general purpose ? 24v bus power ?battery power ? point of load ? embedded processor and i/o supplies figure 1. typical application figure 2. efficiency, sync hronous buck, pfm mode, v out 5v, t a = +25c v out ISL85402 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood 50 55 60 65 70 75 80 85 90 95 100 0.1m 1m 10m 100m 1.0 2.5 efficiency (%) load current (a) 6v v in 12v v in 24v v in 36v v in september 29, 2011 fn7640.0
ISL85402 2 fn7640.0 september 29, 2011 pin configuration ISL85402 (20 ld qfn) top view functional pin descriptions pin name pin # description en 1 the controller is enabled when this pin is left floating or pulled high. the ic is di sabled when this pin is pulled low. range: 0v to 5.5v. fs 2 to connect this pin to vcc, or gnd, or left open will force th e ic to have 500khz switching fr equency. the osc illator switching frequency can also be programmed by adjust ing the resistor from this pin to gnd. ss 3 connect a capacitor from this pin to ground. this capacitor, along with an internal 5a current source, sets the soft-start int erval of the converter. also this pin can be used to track a ramp on this pin. fb 4 this pin is the inverting input of the volt age feedback error amplifier. with a properly selected resistor divider connected fr om v out to fb, the output voltage can be set to any voltage between the power rail (reduced by maximum duty cycle and voltage drop) and the 0.8v reference. loop compensation is achieved by connecting an rc network across comp and fb. the fb pin is also monitored for overvoltage events. comp 5 output of the voltage feedback error amplifier. ilimit 6 programmable current limit pin. with this pin connected to vcc pin, or to gnd, or left open, the current limiting threshold is the set to default 3.6a; the current limiting threshold can be programmed with a resistor from this pin to gnd. mode 7 mode selection pin. pull this pin to gnd for forced pwm mode; to have it floating or connected to vcc will enable pfm mode when the peak inductor current is below the default threshold 700ma . the current boundary threshold between pfm and pwm can also be programmed with a resistor at this pin to ground. chec k for more details in the ?pfm mode operation? on page 12. pgood 8 pgood is an open drain output that will be pulled low immediately under the events when the output is out of regulation (ov or uv) or en pin pulled low. pgood is equipped with a fi xed delay of 1000 cycles upon output power-up (v o > 90%). phase 9, 10 these pins are the phase nodes that should be connected to the output inductor. these pins are connected the source of the high-side n-channel mosfet. ext_boost 11 this pin is used to set boost mode and monitor the battery voltag e that is the input of the boost converter. after vcc por, the controller will detect the voltage on th is pin, if voltage on this pin is below 200mv, the controller is set in synchronous/non-synchr onous buck mode and latch in this state unless vcc is below por falling threshold; if the voltage on this pin after vcc por is above 200mv, the contro ller is set in boost mode and latch in this state. in boost mode the low-side drive r output pwm with same duty cycle with uppe r-side driver to drive the boost switch. in boost mode, this pin is used to monitor input voltage through a resistor divider. by setting the resistor divider, the high threshold and hysteresis can be programmed. when vo ltage on this pin is above 0.8v, the pwm output (lgate) for the boost converter is disabled, and when voltage on this pin is below 0. 8v minus the hysteresis, the boost pwm is enabled. in boost mode operation, pfm is disabled when boost pwm is en abled. check the ?boost converter operation? on page 13 for more details. ss vin phase phase lgate ilimit pgood sgnd en mode fs thermal pad 21 sync com p boot auxvcc vcc ext_boost fb vin 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 pgnd 21 pad
ISL85402 3 fn7640.0 september 29, 2011 sync 12 this pin can be used to synchronize two or more ISL85402 contro llers. multiple ISL85402 can be sy nchronized with their sync pin s connected together. 180 degree phase shift is automatically generated between the master and slave ics. the internal oscillator can also lock to an external frequency source applied on this pin with square pulse waveform (with freq uency 10% higher than the ic?s local frequency, and puls e width higher than 150ns). range: 0v to 5.5v. this pin should be left floating if not used. lgate 13 in synchronous buck mode, this pin is used to drive the lower side mosfet to improve efficiency. in non-synchronous buck when a diode is used as the bottom side power device, this pin should be connected to vcc before vcc startup to have low-side driver (lgate) disabled. in boost mode, it can be used to drive the boost power mosf et. the boost control pwm is same with the buck control pwm. pgnd 14 this pin is used as the ground connection of the po wer flow including driver. conn ect it to large ground plane. boot 15 this pin provides bias voltage to the high-side mosfet driver. a bootstrap circuit is used to create a voltage suitable to driv e the internal n-channel mosfet. the boot charge circuitries are integrated inside of the ic . no external boot diode is needed. a 1f ceramic capacitor is recommended to be used between boot and phase pin. vin 16, 17 connect the input rail to these pins that are connected to the dr ain of the integrated high-side mosfet as well as the source f or the internal linear regulator that provides the bias of the ic. range: 3v to 36v. with the part switching, the op erating input voltage applied to the vin pins must be under 36v. this recommendation allows for short voltage ringing spikes (within a couple of ns time range) due to switching wh ile not exceeding absolute maximum ratings. sgnd 18 this pin provides the return path for the control and monitor portions of the ic. connect it to quite ground plane. vcc 19 this pin is the output of the internal lin ear regulator that supplies the bias for th e ic including the driver. a minimum 4.7f decoupling ceramic capacitor is recommended between vcc to ground. auxvcc 7 this pin is the input of the auxiliary internal linear re gulator which can be supplied by the regulator output after pow er-up. with such configuration, the power dissipation in side of the ic is reduced. the inpu t range for this ldo is 3v to 20v. in boost mode operation, this pin works as boost output overvo ltage detection pin. it detects the boost output through a resist or divider. when voltage on this pin is above 0.8v, the boost pwm disabled; and when voltage on th is pin is below 0.8v minus the hysteresis, the boost pwm is enabled. range: 0v to 20v. pad 21 bottom thermal pad. it is not connected to any electrical potential of the ic. in layout it must be connected to pcb ground cop per plane with area as large as possible to effectively reduce the thermal impedance. functional pin descriptions (continued) pin name pin # description ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL85402irz 85 402irz -40 to +85 20 ld 4x4 qfn l20.4x4c ISL85402eval1z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL85402 . for more information on msl please see techbrief tb363 .
ISL85402 4 fn7640.0 september 29, 2011 block diagram pgood ss fb boot phase (x2) current monitor mode sgnd en fs comp vcc vin 0.8v reference voltage monitor vin (x2) vcc pgnd auxvcc ocp, ovp, otp pfm logic boost mode control slope compensation lgate ilimit auxilary ldo ea comparator oscillator vcc 5a + + power-on reset soft-start logic sync ext_boost gate drive pfm/fpwm bias ldo boot refresh
ISL85402 5 fn7640.0 september 29, 2011 typical application schematic i typical application schematic ii - vcc switch-over to v out typical application schematic iii - boost buck converter (a) synchronous buck (b) non-synchronous buck v out ISL85402 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood v out ISL85402 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood (a) synchronous buck (b) non-synchronous buck v out ISL85402 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood v out ISL85402 vcc sgnd mode boot vin phase pgnd fs ext_boost en fb comp v in auxvcc lgate ilimit ss sync pgood v out ISL85402 vcc sgnd mode boot vin phase pgnd fs pgood en ss fb comp auxvcc lgate ilimit + battery ext_boost sync r1 r2 r3 r4 +
ISL85402 6 fn7640.0 september 29, 2011 absolute maximum rating s thermal information vin, phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +44v vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +6.0v auxvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +22v absolute boot voltage, v boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50.0v upper driver supply voltage, v boot - v phase . . . . . . . . . . . . . . . . . . . +6.0v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to vcc + 0.3v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000v latchup rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma thermal resistance ja (c/w) jc (c/w) ISL85402 qfn 4x4 package (notes 4, 5) . . . . . . 40 3.5 maximum junction temperature (plastic package) . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions supply voltage on v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 36v auxvcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +20v ambient temperature range (industrial). . . . . . . . . . . . . . . . . . -40c to +85c junction temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications refer to ?block diagram? on page 4 and ?typical application schematics? on page 5. operating conditions unless otherwise noted: v in = 12v, or v cc = 4.5v 10%, t a = -40c to +85c. typical are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 6) typ max (note 6) units v in pin supply vin pin voltage range vin pin 3.05 36 v vin pin connected to vcc 3.05 5.5 v operating supply current i q mode = vcc/floating (pfm), no load at the output 300 a mode = gnd (forced pwm), v in =12v, non-switching 1.2 ma standby supply current i q_sby en connected to gnd, v in = 12v 1.8 3 a internal main linear regulator main ldo v cc voltage v cc v in > 5v 4.2 4.5 4.8 v main ldo dropout voltage v dropout_main v in = 4.2v, i vcc = 35ma 0.3 0.5 v v in = 3v, i vcc = 25ma 0.25 0.3 v v cc current limit of main ldo 60 ma internal auxiliary linear regulator auxvcc input voltage range v auxvcc 320 v aux ldo v cc voltage v cc v auxvcc > 5v 4.2 4.5 4.8 v ldo dropout voltage v dropout_aux v auxvcc = 4.2v, i vcc = 35ma 0.3 0.5 v v auxvcc = 3v, i vcc = 25ma 0.25 0.3 v current limit of aux ldo 60 ma aux ldo switch-over rising threshold v auxvcc_rise auxvcc voltage rise; switch to auxiliary ldo 3 3.1 3.2 v aux ldo switch-over falli ng threshold voltage v auxvcc_fall auxvcc voltage fall; switch back to main bias ldo 2.73 2.87 2.97 v aux ldo switch-over hysteresis v auxvcc_hys auxvcc switch-over hysteresis 0.2 v
ISL85402 7 fn7640.0 september 29, 2011 power-on reset rising v cc por threshold v porh_rise 2.82 2.9 3.05 v falling v cc por threshold v porl_fall 2.6 2.8 v v cc por hysteresis v porl_hys 0.3 v enable required enable on voltage v enh 2 v required enable off voltage v enl 0.8 v oscillator pwm frequency f osc r fs = 665k ? 160 200 240 khz r fs = 51.1k ? 1950 2200 2450 khz fs pin connected to vcc or floating or gnd 450 500 550 khz min on time t min_on 130 225 ns min off time t min_off 210 325 ns reference voltage reference voltage v ref 0.8 v system accuracy -1.0 +1.0 % fb pin source current 5na soft-start soft-start current i ss 3 5 7 a error amplifier unity gain-bandwidth c load = 50pf 10 mhz dc gain c load = 50pf 88 db maximum output voltage 3.6 v minimum output voltage 0.5 v slew rate sr c load = 50pf 5 v/s pfm mode control default pfm current threshold mode = vcc or floating 700 ma internal high-side mosfet upper mosfet r ds(on) r ds(on)_up 125 180 m ? low-side mosfet gate driver lgate source resistance 100ma source current 3.5 ? lgate sink resistance 100ma sink current 3.3 ? boost converter control ext_boost boost_off threshold voltage 0.74 0.8 0.86 v ext_boost hysteresis sink current i ext_boost_hys 2.4 3.2 3.8 a auxvcc boost turn-off threshold voltage 0.74 0.8 0.86 v auxvcc hysteresis sink current i auxvcc_hys 2.4 3.2 3.8 a electrical specifications refer to ?block diagram? on page 4 and ?typical application schematics? on page 5. operating conditions unless otherwise noted: v in = 12v, or v cc = 4.5v 10%, t a = -40c to +85c. typical are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
ISL85402 8 fn7640.0 september 29, 2011 power-good monitor overvoltage rising trip point v fb/ v ref percentage of reference point 104 110 116 % overvoltage rising hysteresis v fb/ v ovtrip percentage below ov trip point 3 % undervoltage falling trip point v fb/ v ref percentage of reference point 84 90 96 % undervoltage falling hysteresis v fb/ v uvtrip percentage above uv trip point 3 % pgood rising delay t pgood_delay f osc = 500khz 2 ms pgood leakage current pgood high, v pgood = 4.5v 10 na pgood low voltage v pgood pgood low, ipgood = 0.2ma 0.10 v overcurrent protection default cycle-by-cycle current limit threshold i oc_1 i limit = gnd or vcc or floating 3 3.6 4.2 a hiccup current limit threshold i oc_2 hiccup, i oc_2 /i oc_1 115 % overvoltage protection ov latching-off trip point percentage of reference point lg = ug = latch low 120 % ov non-latching-off trip point p ercentage of reference point lg = ug = low 110 % ov non-latching-off release point p ercentage of reference point 102.5 % over-temperature protection over-temperature trip point 155 c over-temperature recovery threshold 140 c note: 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications refer to ?block diagram? on page 4 and ?typical application schematics? on page 5. operating conditions unless otherwise noted: v in = 12v, or v cc = 4.5v 10%, t a = -40c to +85c. typical are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units performance curves figure 3. efficiency, synchronous buck, forced pwm mode, 500khz, v out 5v, t a = +25c figure 4. efficiency, sync hronous buck, pfm mode, v out 5v, t a = +25c 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.0 0.5 1.0 1.5 2.0 load current (a) 12v v in 24v v in 36v v in 6v v in efficiency (%) 2.5 50 55 60 65 70 75 80 85 90 95 100 0.1m 1m 10m 100m 1.0 2.5 efficiency (%) load current (a) 6v v in 12v v in 24v v in 36v v in
ISL85402 9 fn7640.0 september 29, 2011 figure 5. line regulation, v out 5v, t a = +25c figure 6. load regulation, v out 5v, t a = +25c figure 7. efficiency, synchronous buck, forced pwm mode, 500khz, v out 3.3v, t a = +25c figure 8. efficiency, sync hronous buck, pfm mode, v out 3.3v, t a = +25c figure 9. input quiescent current under no load, pfm mode, v out = 5v figure 10. ic die temperature under +25c ambient temperature, still air, 500khz, i o = 2a performance curves (continued) 4.950 4.952 4.954 4.956 4.958 4.960 4.962 4.964 4.966 4.968 4.970 0 5 10 15 20 25 30 36 input voltage (v) v out (v) i o = 2a i o = 0a i o = 1a 4.950 4.952 4.954 4.956 4.958 4.960 4.962 4.964 4.966 4.968 4.970 0.0 0.5 1.0 1.5 2.0 2.5 load current (a) 6v v in 12v v in 24v v in 36v v in v out (v) 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.0 0.5 1.0 1.5 2.0 2.5 efficiency (%) load current (a) 6v v in 12v v in 24v v in 36v v in 1m 10m 100m 1.0 2.5 load current (a) efficiency (%) 0.1m 6v v in 12v v in 24v v in 36v v in 40 45 50 55 60 65 70 75 80 85 90 95 100 0 20 40 60 80 100 120 140 160 180 200 -50-25 0 255075100125 input current (a) ambient temperature (c) v in = 24v v in = 12v 25 30 35 40 45 50 55 60 65 70 75 80 85 0 5 10 15 20 25 30 35 40 v in (v) v o = 12v v o = 5v v o = 20v ic die temperature (c)
ISL85402 10 fn7640.0 september 29, 2011 figure 11. ic die temperature under +25c ambient temperature, still air, 500khz, i o = 2.5a figure 12. synchronous buck mode, v in 36v, i o 2a, enable on figure 13. synchronous buck mode, v in 36v, i o 2a, enable off figure 14. v in 36v, prebiased start-up figure 15. synchronous buck with force pwm mode, v in 36v, i o 2a figure 16. v in 24v, 0 to 2a step load, force pwm mode performance curves (continued) 25 30 35 40 45 50 55 60 65 70 75 80 85 0 5 10 15 20 25 30 35 40 v in (v) v o = 12v v o = 5v v o = 20v ic die temperature (c) v out 2v/div 2ms/div phase 20v/div v out 2v/div 2ms/div phase 20v/div v out 2v/div 2ms/div phase 20v/div v out 20mv/div (5v offset) phase 20v/div 5s/div v out 100mv/div (5v offset) i out 1a/div phase 20v/div 1ms/div
ISL85402 11 fn7640.0 september 29, 2011 figure 17. v in 24v, 80ma load, pfm mode figure 18. v in 24v, 0 to 2a step load, pfm mode figure 19. non-synchronous buck, force pwm mode, v in 12v, no load figure 20. non-synchronous buck, force pwm mode, v in 12v, 2a figure 21. boost buck mode, boost input step from 36v to 3v, v out buck = 5v, i out _buck = 1a figure 22. boost buck mode, boost input step from 3v to 36v, v out buck = 5v, i out _buck = 1a performance curves (continued) v out 1v/div 100s/div v out 70mv/div (5v offset) lgate 5v/div phase 20v/div i out 1a/div 1ms/div v out 200mv/div (5v offset) lgate 5v/div phase 20v/div phase 5v/div 20s/div v out 10mv/div (5v offset) 5s/div v out 10mv/div (5v offset) phase 10v/div 20ms/div phase_boost 10v/div v in _boost_input 5v/div phase_buck 10v/div v out buck 100mv/div (5v offset) 10ms/div phase_boost 10v/div v in _boost_input 5v/div phase_buck 10v/div v out buck 100mv/div (5v offset)
ISL85402 12 fn7640.0 september 29, 2011 functional description initialization initially the ISL85402 continually monitors the voltage at en pin. when the voltage on en pin exceed s its rising on threshold, the internal ldo will start up to build up vcc. after power-on reset (por) circuits detect that vcc voltage has exceeded the por threshold, the soft-start will be initiated. soft-start the soft-start (ss) ramp is built up in the external capacitor on the ss pin that is charged by an internal 5a current source. the ss ramp starts from 0 to vo ltage above 0.8v. once ss reaches 0.8v, the bandgap reference takes over and ic gets into steady state operation. the ss plays a vital role in the hiccup mode of operation. the ic works as cycle-by-cycle peak curren t limiting at over load condition. when a harsh con dit on occurs and the current in upper side mosfet reach the second overcurrent threshold, the ss pin is pulled to ground and a dummy soft-start cycle is initiated. at dummy ss cycle, the current to charge soft-sta rt cap is cut down to 1/5 of its normal value. so a dummy ss cycle takes 5x of the regular ss cycle. during the dummy ss period, the co ntrol loop is disabled and no pwm output. at the end of this cycle, it will start the normal ss. the hiccup mode persist until the seco nd overcurrent threshold is no longer reached. the ISL85402 is capable of starti ng up with prebiased output. pwm control pulling the mode pin to gnd will set the ic in forced pwm mode. the ISL85402 employ the peak curre nt mode pwm control for fast transient response and cycle-by-cycle current limiting. see ?block diagram? on page 4. the pwm operation is initialized by the clock from the oscillator. the upper mosfet is turned on by the clock at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current sense signal an d the slope compensation signal reaches the error amplifier ou tput voltage level, the pwm comparator is trigger to shut do wn the pwm logic to turn off the high-side mosfet. the high-side mosfet stays off until the next clock signal comes for next cycle. the output voltage is sensed by a resistor divider from v out to fb pin. the difference between fb voltage and 0.8v reference is amplified and compensated to generate the error voltage signal at comp pin. then the comp pin signal is compared with the current ramp signal to shut down the pwm. pfm mode operation to pull the mode pin high (>2.5v) or leave the mode pin floating will set the ic to have pfm (pul se frequency modulation) operation in light load. in pfm mode, the sw itching frequency is dramatically reduced to minimize the switchin g loss. the ISL85402 enters pfm mode when the mosfet peak current is lower than the pwm/pfm boundary current threshold. this threshold is 700ma as default when there is no programm ing resistor at mode pin. the current threshold for pwm/pfm boundary can be programmed by choosing the mode pin resistor value calculated from equation 2, where ipfm is the desired pwm/pfm boundary current threshold and r mode is the programming resistor. figure 23. boost buck mode, v o = 9v, i o = 1.8a, boost input drops from 16v to 9v dc performance curves (continued) v out 5v/div phase_boost 20v/div 10ms/div il_boost 2a/div phase_buck 20v/div c ss f [] 6.5 t ss s [] ? = (eq. 1) r mode 118500 ipfm 0.2 + ---------------------------------------- = (eq. 2)
ISL85402 13 fn7640.0 september 29, 2011 synchronous and non-synchronous buck the ISL85402 supports both synchronous and non-synchronous buck operations. for a non-synchronous buck operation when a power diode is used as the low-side power device, the lgate driver can be disabled with lgate connected to vcc (before ic start-up). input voltage with the part switching, the op erating ISL85402 input voltage must be under 36v. this recommendation allows for short voltage ringing spikes (within a co uple of ns time range) due to part switching while not exceeding the 44v as absolute maximum ratings. output voltage the ISL85402 output voltage can be programmed down to 0.8v by a resistor divider from v out to fb. the maximum achievable voltage is (v in *d max - v drop ), where v drop is the voltage drop in the power path including mainly the mosfet r ds(on) and inductor dcr. the maximum duty cycle d max is decided by (1/fs - t min(off) ). output current with the high-side mosfet integrated, the maximum output current, which the ISL85402 can supp ort is decided by the package and many operating conditions. thus , including input voltage, output voltage, duty cycle, switching frequency and temperature, etc. note the following points. ? the maximum dc output current is 5a limited by the package. ? from the thermal perspective, the die temperature shouldn?t exceed +125c with the power lo ss dissipated inside of the ic. figures 10 and 11 show the thermal performance of this part operating at different conditions. figures 10 and 11 shows 2a an d 2.5a applications under +25c still air conditions over v in range. the temperature rise data in these figures can be used to estimate the die temperature at different ambient temperatures under various operating conditions. note that more temperature rise is expected at higher ambient temperature due to more conduction loss caused by r ds(on) increase. generally, the part can output 2.5a in typical application condition v in 8~30v, v o 5v, 500khz, still air and +85c ambient conditions. for any other operating conditions, refer to the previous mentioned thermal curves to estimate the maximum output current. the output current should be derated under any conditions causing the die temperature exceeding +125c. basically, the die temperature equals to the sum of ambient temperature and the temperature rise resulting from the power dissipated the ic package with a certain junction to ambient thermal impedance ja . the power dissipated in the ic is related to the mosfet switching loss, conduction loss and the internal ldo loss. besides the load, these losses are also related to input voltage, output voltage, duty cycle, switching frequency and temperature. with exposed pad at bottom, the heat of the ic mainly goes through the bottom pad and ja is greatly reduced. the ja is highly related to layout and air flow conditions. in layout, multiple vias ( 9) are strongly recommended in the ic bottom pad. and the bottom pad with its vias should be placed in ground copper plane with area as large as possible multiple layers. the ja can be reduced further with air flow. refer to figures 8 and 9 for the thermal performance with 100 cfm air flow. boost converter operation ?typical application schematic iii - boost buck converter? on page 5, shows the circuits where the boost works as a pre-stage to provide input to the following buck stage. this is for applications when the input voltage could drop to a very low voltage in some constants (in some battery powered systems as for example), causing the output voltage drops out of regulation. the boost converter can be enabled to boost the input voltage up to keep the output voltage in regulation. when system input voltage recovers back to normal, the boost stage is disabled while only the buck stage is switching. ext_boost pin is used to set b oost mode and monitor the boost input voltage. at ic start-up before soft-start, the controller will be latched in boost mode when the voltage is on above 200mv; it will latch in synchronous buck mode if voltage on this pin is below 200mv. in boost mode the low-si de driver output pwm has the same pwm signal with the buck regulator. in boost mode, the ext_boost pin is used to monitor boost output voltage to turn on and turn off the boost pwm. the auxvcc pin is used to monitor the boost output voltage to turn on and turn off the boost pwm. referring to figure 25 on page 14, a resistor divider from boost input voltage to ext_boost pin is used to detect the boost input voltage. when the voltage on ext_boost pin is below 0.8v, the boost pwm is enabled with a fixed 500s soft-start and the boost duty cycle increase linearly from t min(on) *fs to ~50%, and a 3a sinking current is enabled at ext_ boost pin for hysteresis purpose. when the voltage on the ext_boost pin recovers to be above 0.8v, the boost pwm is disabled immediat ely. use equation 3 to calculate the upper resistor r up (r1 in figure 25) for a desired hysteresis v hys at boost input voltage. use equation 4 to calculate the lower resistor r low (r2 in figure 25) according to a desired boost enable threshold. 0 100 200 300 400 500 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 r mode (k ? ) i pfm (a) figure 24. r mode vs i pfm r up m [] vhys 3 a [] ---------------------- = (eq. 3) r low r up 0.8 ? vfth 0.8 ? --------------------------------------- = (eq. 4)
ISL85402 14 fn7640.0 september 29, 2011 where vfth is the desired falling threshold on boost input voltage to turn on the boost, 3a is the hysteresis current, and 0.8v is the reference voltage to be compared with. note the boost start-up threshold has to be selected in a way that the buck is operating working well and kept in close loop regulation before boost start-up. otherwise, large in-rush current at boost start-up could occur at boost input due to the buck open loop saturation. similarly, a resistor divider from boost output voltage to auxvcc pin is used to detect the boost output voltage. when the voltage on auxvcc pin is below 0.8v, the boost pwm is enabled with a fixed 500s soft-start, and a 3a sinking current is enabled at auxvcc pin for hysteresis purposes. when the voltage on the auxvcc pin recovers to be above 0.8v, the boost pwm is disabled immediately. use equation 3 to calculate the upper resistor r up (r 3 in figure 25) according to a desired hysteresis v hy at boost output voltage. use equation 4 to calculate the lower resistor r low (r 4 in figure 25) according to a desired boost enab le threshold at boost output. assuming v bat is the boost input voltage, v outbst is the boost output voltage and v out is the buck output voltage, the steady state transfer function are: from equations 5 and 6, equation 7 can be derived to estimate the steady state boost output voltage as function of v bat and v out : after the ic starts up, the boost buck converters can keep working when the battery voltage drops extremely low because the ic?s bias (vcc) ldo is powered by the boost output. for example, a 3.3v output application, battery drops to 2v, vin pin voltage is powered by the boost output voltage that is 5.2v (equation 7), meaning the vin pin (buck input) still sees 5.2v to keep the ic working. note in the previous mentioned case, the boost input current could be high because the input voltage is very low (v in *i in =v out *i out *efficiency). if the design is to achieve the low input operation with full load, the inductor and mosfet have to be selected to be with enough current ratings to handle the high current appearing at boost input. the boost inductor current are the same with the boost input current, which can be estimated as equation 8, where p out is the output power, v bat is the boost input voltage, eff is the estimated efficiency of the whole boost and buck stages. based on the same concerns of boos t input current, the ic should be disabled before the boost input vo ltage rise above a certain level. pfm is not available in boost mode. oscillator and synchronization the oscillator has a default freq uency of 500khz with fs pin connected to vcc, or ground, or floating. the frequency can be programmed to any frequency between 200khz and 2.2mhz with a resistor from fs pin to gnd. figure 25. boost converter control auxvcc lgate + battery ext_boost + logic pwm lgate drive 0.8v 0.8v i_hys = 3a i_hys = 3a vout_bst r3 r4 r1 r2 v outbst 1 1d ? ------------------ v bat ? = (eq. 5) v out dv outbst ? d 1d ? ------------------ v bat ? == (eq. 6) v outbst v bat v out + = (eq. 7) il in p out v bat eff ? -------------------------------------- = (eq. 8) r fs k [] 145000 16 fs ? khz [] ? fs khz [] ------------------------------------------------------------------------------------ = (eq. 9)
ISL85402 15 fn7640.0 with the sync pins si mply connected together , multiple ISL85402s can be synchronized. the slave ics automatically have 180 phase shift with respective to the master ic. with an external square pulse wa veform (with frequency 10% higher than the local frequency, 10% to 90% duty cycle and pulse width higher than 150ns) on sync pin. thus, the ISL85402 will synchronize its switching frequency to the fundamental frequency of the input waveform. the internal oscillator synchronizes with the leading edge of the input signal. the rising edge of ugate pwm is delayed by 180 from the leading ed ge of the external clock signal. fault protection overcurrent protection the overcurrent function protects against any over load condition and output short at worst case, by monitoring the current flowing through the upper mosfet. there are 2 current limiting thresholds. the first one i oc1 is to limit the high-side mosfet peak current cycle-by-cycle. the current limit threshold is set to default at 3.6a with ilimit pin connected to gnd or vcc, or left open. the current limit threshold can also be programmed by a resistor r lim at ilimit pin to ground. use equation 10 to calculate the resistor. note that ioc1 is higher with lower r lim . ioc1 reaches its maximum 5.4a with r lim at 54.9k (typ). with r lim lower than 54.9k (typ), the oc limit goes to its default value of 3.6a (typ). the second current protection threshold i oc2 is 15% higher than i oc1 mentioned previously. upon inst ant when the high-side mosfet current reaches i oc2 , the pwm is shut off after 2-cycle delay and the ic enters hiccup mode. in hiccup mode, the pwm is disabled for dummy soft-start duration equaling to 5 regular soft-start periods. after this dummy soft-start cycle, the true soft-start cycle is attempted again. the i oc2 offers a robust and reliable protections against the worst case conditions. the frequency foldback is implemented for the ISL85402. when overcurrent limiting, the switching frequency is reduced to be proportional to output voltage in order to keep the inductor current under limit threshold during overlo ad condition. the low limit of frequency under frequency foldback operation is 40khz. overvoltage protection if the voltage detected on the fb pin is over 110% of reference, the high-side and low-side driver shuts down immediately and won?t be allowed on until fb voltage drops to 0.8v. when the fb voltage drops to 0.8v, the drivers are released to on. if the 120% overvoltage threshold is reached, the high-side and low-side driver shuts down immediately and the ic is latched off. the ic has to be reset for restart. thermal protection the ISL85402 pwm will be disabled if the junction temperature reaches +155c. a +15c hysteresis in sures that the device will not restart until the junction temperature drops below +140c. component selections output capacitors output capacitors are required to filter the inductor current and supply the load transient current. all ceramic output capacitors are achievable with this ic. also in some applications, the aluminum el ectrolytic type capacitors are added to the output to provide be tter load transient and longer holdup time for the load. when low cost, high esr aluminum capacitor is used at output, a ceramic capacitor (2.2f to 10f) is recommended to handle the ripple current and reduce the total equivalent esr effectively. input capacitors depending on the system input power rail conditions, the aluminum electrolytic type capacitor is normally needed to provide the stable input voltage. thus, restrict the switching frequency pulse current in small area over the input traces for better emc performance. the input capacitor should be able to handle the rms current from the switching power devices. ceramic capacitors must be used at vin pin of the ic and multiple capacitors including 1f and 0.1f are recommended. place these capacitors as closely as possible to the ic. 0 200 400 600 800 1000 1200 0 500 1000 1500 2000 2500 f s (khz) r fs (k ? ) figure 26. r fs vs frequency r lim 300000 i oc a [] 0.018 + ------------------------------------------------------ = (eq. 10) figure 27. r lim vs ioc1 70 120 170 220 270 320 370 0.0 1.0 2.0 3.0 4.0 5.0 6.0 r lim (k ? ) i oc1 (a)
ISL85402 16 fn7640.0 buck output inductor generally the inductor should filter the current ripple to be 30~50% of the regulator?s maximum average output current. the low dcr inductor should be selected for the highest efficiency and the inductor satura tion current rating should be higher than the highest transient expected. low-side power mosfet in synchronous buck application, a power n-mosfet is needed as the synchronous low-side mosf et and it must have low r ds(on) , low r g (r g_typ < 1.5 ? recommended ) , v gth (v gth_min 1.2v) and q gd . a good example is bsz100n06ls3g. output voltage feedback resistor divider the output voltage can be programmed down to 0.8v by a resistor divider from v out to fb according to equation 11. in an application requiring least input quiescent current, large resistors should be used for the divider. 232k is recommended for the upper resistor. compensation network with peak current mode control, type ii compensation is normally used for most of the applications . but in applications to achieve higher bandwidth, type iii is better. note that in an application wher e pfm mode is desired and type iii compensation network is used, the value of the capacitor between comp pin and fb pin (not the capacitor in series with the resistor between comp and fb ) should be minimal to reduce the noise coupling for proper pfm operations. 10pf is recommended for this capacitor between comp and fb at pfm applications. thus, a capacitor (<1n f) at fb pin to ground helps the proper pfm mode operation. boost inductor besides the need to sustain the current ripple to be within a certain range (30% to 50%), the boost inductor current at its soft-start is a more important pe rspective to be considered in selection of the boost inductor. each time the boost starts up, there is a fixed 500s soft-start time when the duty cycle increases linearly from t min(on) *fs to ~50%. before and after boost start-up, the boost output voltage will jump from v in_boost to voltage (v in_boost + v out_buck ). the design target in boost soft-start is to ensure the boost input current is sustained to minimum but capable to charge the boost output voltage to have a voltage step equaling to v out_buck . a big inductor will block the inductor current to increase and not high enough to be able to charge the output capacitor to the final steady state value (v in_boost + v out_buck ) within 500s. a 6.8h inductor is a good starting point for its selection in design. the boost inductor current at start-up must be checked by oscilloscope to ensure it is under acceptable range. boost output capacitor based on the same theory in boost start-up described previously in boost inductor selection, a larg e capacitor at boost output will cause high in-rush current at boost pwm start-up. 22f is a good choice for applications with buck output voltage less than 10v. also some minimum amount of capacitance has to be used in boost output to keep the system stable. layout suggestions 1. put the input ceramic capacitors at the closest place to the ic vin pin and power ground connecting to power mosfet or diode. keep this loop (input ceramic capacitor, ic vin pin and mosfet/diode) as tiny as possible to achieve the least voltage spikes induced by the trace parasitic inductance. 2. put the input aluminum capacitors close to ic vin pin. 3. keep the phase node copper area small but large enough to handle the load current. 4. put the output ceramic and aluminum capacitors also close to the power stage components. 5. put vias ( 9) in the bottom pad of the ic. the bottom pad should be placed in ground copper plane with area as large as possible in multiple layers to effectively reduce the thermal impedance. 6. put the 4.7f ceramic decoupling capacitor at vcc pin the closest place to the ic. and put multiple vias ( 3) right close to the ground pad of this capacitor. 7. keep the bootstrap capacitor close to the ic. 8. keep the lgate drive trace as short as possible and try to avoid use via in lgate drive path to achieve the lowest impedance. 9. put the positive voltage sense trace close to the place to be strictly regulated. 10. put all the peripheral control components close to the ic. v out 0.8 1 r up r low --------------------- + ?? ?? ?? ? = (eq. 11) figure 28. pcb via pattern
ISL85402 17 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7640.0 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL85402 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 9/29/2011 fn7640.0 initial release
ISL85402 18 fn7640.0 package outline drawing l20.4x4c 20 lead quad flat no-lead plastic package rev 0, 11/06 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance: decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view bottom view side view 4.00 a 4.00 b 6 pin 1 index area (4x) 0.15 4x 0.50 2.0 16x 20 16 15 11 pin #1 index area 6 2 .70 0 . 15 5 1 20x 0.25 +0.05 / -0.07 0.10 m ab c 20x 0.4 0.10 4 6 10 base plane seating plane 0.10 see detail "x" 0.08 c c c 0 . 90 0 . 1 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 8 typ ) ( 2. 70 ) ( 20x 0 . 6) ( 20x 0 . 5 ) ( 20x 0 . 25 )

▲Up To Search▲

Price & Availability of ISL85402

	To Download ISL85402 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .